Sphinx Verilog Diagrams¶

sphinx-verilog-diagrams is an extension to Sphinx to make it easier to write nice documentation from Verilog files.

You use the .. verilog-diagram RST directive to generate various styles of diagrams from verilog code.

Most of the time there will be a license header at the top of source code, which we might not want to show in the documentation. This extension also provides the .. no-license RST directive which works exactly like the .. literalinclude directive, but the lines option is overridden to only show the lines after the license header.

The project repository is hosted on GitHub.

Installation¶

Python 3.5+ is required.

pip install sphinxcontrib-verilog-diagrams

Or,

python3 -m pip install sphinxcontrib-verilog-diagrams

Sphinx integration¶

In your conf.py, add the following lines.

extensions = [
   ...,
   'sphinxcontrib_verilog_diagrams',
]

Non-python dependencies¶

These dependencies can either be installed on your system or you can install them using the conda environment.yml file.

yosys (required)
netlistsvg (optional)

Usage¶

The verilog-diagram RST directive can be used to generate a diagram from Verilog code and include it in your documentation.

.. verilog-diagram:: file.v
   :type: XXXXX
   :module: XXXX
   :flatten:

Options¶

:type: - Verilog Diagram Types;

yosys-blackbox - Netlist rendered by Yosys.
yosys-aig - Verilog file run through aigmap before image is generated directly in Yosys.
netlistsvg - Render output with netlistsvg

:module: - Which module to diagram.

:flatten: - Use the Yosys flatten command before generating the image.

Examples¶

Single DFF¶

Verilog Code Block (with license header)¶

RST Directive¶

.. literalinclude:: verilog/dff.v
   :language: verilog
   :linenos:
   :caption: verilog/dff.v

Result¶

verilog/dff.v¶

/*
 * Copyright (C) 2020  The SymbiFlow Authors.
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 *     https://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 *
 * SPDX-License-Identifier: Apache-2.0
 */

// Single flip-flip test.
module top(input clk, input di, output do);
  always @( posedge clk )
    do <= di;
endmodule // top

Verilog Code Block (without license header)¶

RST Directive¶

.. no-license:: verilog/dff.v
   :language: verilog
   :linenos:
   :caption: verilog/dff.v

Result¶

verilog/dff.v¶

// Single flip-flip test.
module top(input clk, input di, output do);
  always @( posedge clk )
    do <= di;
endmodule // top

Yosys BlackBox Diagram¶

RST Directive¶

.. verilog-diagram:: verilog/dff.v
   :type: yosys-bb

Result¶

Yosys AIG Diagram¶

RST Directive¶

.. verilog-diagram:: verilog/dff.v
   :type: yosys-aig

Result¶

NetlistSVG Diagram¶

RST Directive¶

.. verilog-diagram:: verilog/dff.v
   :type: netlistsvg

Result¶

Combinational Full Adder¶

Verilog Code¶

RST Directive¶

.. no-license:: verilog/adder.v
   :language: verilog
   :linenos:
   :caption: verilog/adder.v

Result¶

verilog/adder.v¶

module ADDER (
	a, b, cin,
	sum, cout
);
	input wire a;
	input wire b;
	input wire cin;

	output wire sum;
	output wire cout;

	// Full adder combinational logic
	assign sum = a ^ b ^ cin;
	assign cout = ((a ^ b) & cin) | (a & b);
endmodule

Yosys BlackBox Diagram¶

RST Directive¶

.. verilog-diagram:: verilog/adder.v
   :type: yosys-bb
   :module: ADDER

Result¶

Yosys AIG Diagram¶

RST Directive¶

.. verilog-diagram:: verilog/adder.v
   :type: yosys-aig
   :module: ADDER

Result¶

NetlistSVG Diagram¶

RST Directive¶

.. verilog-diagram:: verilog/adder.v
   :type: netlistsvg
   :module: ADDER

Result¶

NetlistSVG Demos¶

CARRY4 defined directly¶

verilog/carry4-whole.v¶

module CARRY4(output [3:0] CO, O, input CI, CYINIT, input [3:0] DI, S);
  assign O = S ^ {CO[2:0], CI | CYINIT};
  assign CO[0] = S[0] ? CI | CYINIT : DI[0];
  assign CO[1] = S[1] ? CO[0] : DI[1];
  assign CO[2] = S[2] ? CO[1] : DI[2];
  assign CO[3] = S[3] ? CO[2] : DI[3];
endmodule

.. verilog-diagram:: verilog/carry4-whole.v
   :type: netlistsvg
   :module: CARRY4
   :caption: carry4-whole.v

carry4-whole.v¶

CARRY4 defined by components¶

verilog/carry4-bits.v¶

`include "muxcy.v"
`include "xorcy.v"

module CARRY4(output [3:0] CO, O, input CI, CYINIT, input [3:0] DI, S);
   wire CIN = CI | CYINIT;

   MUXCY muxcy0 (.O(CO[0]), .CI(CIN),   .DI(DI[0]), .S(S[0]));
   MUXCY muxcy1 (.O(CO[1]), .CI(CO[0]), .DI(DI[1]), .S(S[1]));
   MUXCY muxcy2 (.O(CO[2]), .CI(CO[1]), .DI(DI[2]), .S(S[2]));
   MUXCY muxcy3 (.O(CO[3]), .CI(CO[2]), .DI(DI[3]), .S(S[3]));

   XORCY xorcy0 (.O(O[0]), .CI(CIN),   .LI(S[0]));
   XORCY xorcy1 (.O(O[1]), .CI(CO[0]), .LI(S[1]));
   XORCY xorcy2 (.O(O[2]), .CI(CO[1]), .LI(S[2]));
   XORCY xorcy3 (.O(O[3]), .CI(CO[2]), .LI(S[3]));
endmodule

verilog/muxcy.v¶

module MUXCY(output O, input CI, DI, S);
  assign O = S ? CI : DI;
endmodule

verilog/xorcy.v¶

module XORCY(output O, input CI, LI);
  assign O = CI ^ LI;
endmodule

MUXCY¶

.. verilog-diagram:: verilog/muxcy.v
   :type: netlistsvg
   :caption: muxcy.v
   :module: MUXCY

muxcy.v¶

XORCY¶

.. verilog-diagram:: verilog/xorcy.v
   :type: netlistsvg
   :caption: xorcy.v
   :module: XORCY

xorcy.v¶

CARRY4 without flatten¶

.. verilog-diagram:: verilog/carry4-bits.v
   :type: netlistsvg
   :module: CARRY4
   :caption: carry4-bits.v without flatten

carry4-bits.v without flatten¶

CARRY4 with flatten¶

.. verilog-diagram:: verilog/carry4-bits.v
   :type: netlistsvg
   :module: CARRY4
   :flatten:
   :caption: carry4-bits.v with flatten

carry4-bits.v with flatten¶